• MI01

Basics for computer architecture, 60 to 80 students, success rate 86% (2019), students satisfaction 91% (2022)

• MI12

This module presents System design engineering, with a focus on architecture design, architecture exploration, timing constraints, etc. 18 students, success rate 90% (2022), students satisfaction 84% (2022). Students work on a mini-project during 4 hours of weekly lab. Projects are about design and validation of functions related to sensors; Smartphones sensors (Android), Kinect interfacing, etc.

• Member of TTD committee, Agence Nationale de la Recherche (2011–2014)
• Member of VTT committee, Agence Nationale de la Recherche (2008 — 2011)
• Deputy scientific Director, competitivity Cluster iTrans (2008–2012)
• Co-animator of working group “Diagnosability”, Competitivity Cluster System@tic (2006–2010)
• Board Member of University of Technology of Compiègne (2003–2006)

Conference organizing committees

Regularly member of scientific Committee and REVIEWER for:

• ACM transactions on embedded computing systems — ACM Symposium on Parallel Algorithms and Architectures (SPAA) — Techniques et Sciences Informatiques (TSI) — ITSC (Intelligent Transport Systems Consortium)
• CITEI 2020 (Conference on Internet of Things and Embedded Intelligence)

Quick bio

• M. Shawky is currently full professor with Costech laboratory (Connaissance Organisation et Systèmes TECHniques), and teaching at Department of Computer Science, Université de Technologie de Compiègne (UTC), Compiègne, France.
• M. Shawky received his MSc and PhD respectively in 1989 and 1992 on distributed computing (UTC). His research interests currently include model extraction by machine learning, traceability and proof of decisions.
• He is author and co-author of more than 120 international research publications. He is responsible of several European, industrial, national and regional research projects. He is co-coordinating the Work Group “Robust Design” for the European Institute EICOSE. He is also on the list of the evaluators for European Research Program INCO.

Habilitation to Direct Research, 2004

From multiprocesseur parallelism to reconfigurable computing, at Heudiasyc laboratory, Joint Research Unit with CNRS , Université de Technologie de Compiègne.

• Defended on November 25, 2004, before the jury composed of M. Akil, J.M. Delosme, et M. Paindavoine referees, B. Dubuisson, D. Meizel, et Y. Sorel examinators.

PHD Thesis, 1989–1992

Parallel architectures, vision and autonomous vehicles, study and development, Heudiasyc Laboratory, URA CNRS 827, Université de Technologie de Compiegne. The objective was to design and develop a multiprocessor computing platform for a mobile robot. PhD supervisor : Kun Mean HOU. Defended on December 12, 1992, before the jury: G. Fontenier et P. Mérieux referees, B. Dubuisson President, K.M. Hou, Xiao Wei TU examinators.

M. Sc. Thesis, 1988–1989

Systems control, Heudiasyc Laboratory, CNRS, Université de Technologie de Compiègne automatic generation of Image and text bundles (by graphics vectorization) System Control speciality

Engineering diploma, 1981–1986

• B.Sc. with honors Electronics and telecommunication, control option.
• Graduation project at Institüt für Nächrichtentechnik, RWTH, Aachen, Germany, about descriptive coding of images for compression purpose.
• Mid cursus Internships at Siemens AG, Graz, Austria, on design of automata networks, and at Merlin Gérin S.A., Grenoble, France, assembling the heart of ST-CM2 circuit breaker.

Professional Employment History

• 2010 — … Full university professor, Computer Science Dept., Université de Technologie de Compiègne (UTC), France
• 2000 Visiting asso­ciate professor, Systems Design Engineering, Waterloo University, Ontario, Canada
• 1997 — 2004 Asso­ciate professor, Computer Science Dept., UTC
• 1993 — 1997 Asso­ciate professor, Complex Systems Lab, University of Evry, France
• 1992 — 1993 Assistant professor, UTC, France
• 1988 — 1992 M.Sc. and PhD thesis, Parallel computing for autonomous vehicles, UTC, France.
• 1985 – 1987 Electronic design Engineer with Fanuc Inc.